Communications equipment e.g., routers and switches, are now required to move data packets in a Tbps (Tera or 1012 bits per second) range and soon beyond. To achieve such a level of performance those communications devices uses many multi-Gbps (Giga or 109 bits per second) high speed serial links. The standard being now a 2.5 Gbps link. Thousands of such links are thus required to convey data packets IN and OUT of a Tbps-class switch fabric. Because of the speeds involved serial links are using, in most applications, a code, such as a 8B/10B DC balanced code, to improve the transmission characteristics yet at the expense of a 20% overhead which reduces the effective data rate to 2.0 Gbps. Because the technology (generally CMOS) is used at its upper limit of operation and due to the huge amount of moved data, the probability of an error occurrence is becoming too high. Even though a link can be specified with a 10−15 BER (bit error rate), an already exceptionally good value, an error would however potentially occurs every 8 nm or so. Indeed, in a Tbps switch, moving 1012 bits IN and OUT at every second, the 1015 level thus, a probability of 1 to get an error, is reached every 500 seconds i.e., 8 minutes. This is clearly unacceptable.
Moreover, technology itself, i.e., the ASICs (application specific integrated circuits) used to implement the switching functions, are subject to ‘soft’ errors as a result of the extreme miniaturization of their memory elements. Hence, new designed equipment tend to incorporate ECC (error correcting codes) in order to correct, on-the-fly, occasional errors to obtain a MTBF (mean time between failure) compatible with the domain of applications considered by the invention i.e., data communications networks for multipurpose services (data and voice) where the level of expectation is very high since this type of equipment is assumed to work, error-free, 24 hours a day and 7 days a week.
The 8B/10B code as described in U.S. Pat. No. 4,486,739 from IBM untitled ‘Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code’, 1984, by Franaszek and Widmer is well adapted to the transmission of digital signals over high-speed i.e., multi-Gbps, serial links used in numerous instances of communications equipment which are now required to cope with aggregate data throughput expressed in Tera or 1012 bps. This code has been specified as a standard by ANSI i.e., the American National Standards Institute. While 8B/10B was first used by the ANSI FiberChannel FC-1 layer transmission protocol, including serial encoding and decoding to and from the physical layer, special characters, and error control; it has since been more largely adopted e.g., for the Gigabit version of Ethernet. Encoding data transmitted at high speeds provides some advantages. 8B/10B code is DC balance thus, encoding limits the effective transmission characteristics, such as the ratio of 1 s to 0 s, on the error rate. Bit-level clock recovery of the receiver can be greatly improved by using data encoding. Also, encoding can help distinguish data bits from control bits. However, this is because 8B/10B encoding increases the possibility that the receiving station can detect and correct transmission or reception errors that it is considered by the invention. Indeed, the code is designed so that the transmission digit errors on the serial links are always confined to the 6B or 4B sub-blocks in which they occur and generate decoded error bursts no longer than 5 or 3, respectively, from a single line digit error. Sub-blocks result from the fact that 8B/10B code is, as above patent title suggests, a partitioned code. This means that each byte is actually composed of two separate 5B/6B and 3B/4B codes. This significantly contributes to reduce error spreading after decoding.
Much more on 8B/10B code can be found in the here above cited US patent and in other publications on this subject. Among them, one may want to refer to an IBM research report published by the IBM Thomas J. Watson Research Center, Yorktown Heights, N.Y. 10598, the USA, ‘The ANSI Fibre Channel transmission Code’ by Albert X. Widmer, under reference RC-18855, dated April 1993. Thus, 8B/10B code was devised with the objective, among other things, to ease error correction in preventing single line digit error from spreading in more than 5-bit bursts after decoding.
As mentioned in the above referred patent i.e., U.S. Pat. No. 4,486,739, the Fire codes, which are cyclic codes, can be used with very good correcting results on the 8B/10B encoded packets. Fire codes are burst-error-correcting codes thus, are well adapted to cope with the kind of errors occurring on the electrical links as described above i.e., in bursts spanning several contiguous bits after decoding. They can also take care of the soft errors of the ASIC devices used to implement the switching function since soft errors generally affect a single bit i.e., a binary latch or a single bit of a RAM (random access memory). A description of Fire codes can easily be found in the abundant literature on ECC. Among many examples, one can refer to ‘Error Control Coding’, a book by Shu LIN and Daniel J. Costello, Prentice-Hall, 1983, ISBN 0-13-283796-X and more specifically to chapter 9 on ‘Burst-Error-Correcting Codes’. The use of such Fire codes has however drastic practical limitations. If they are actually able of correcting a single burst of errors their detect ability of errors spreading on more bits is however poor.
Similarly, Burton codes, which are specific Fire codes, have a better level of correct ability than Fire codes however, at the expense of an even lower level of detection when errors spread on more bits than what they can normally correct.